1. Field of the Invention
The present invention generally relates to computer hardware and more specifically to a system and method for reducing crosstalk in on-chip networks.
2. Description of the Related Art
A modern computer chip, such as a central processing unit (CPU) or a graphics processing unit (GPU), generally includes a communication network that couples each chip component with other chip components and allows data to be transmitted between those various components. The communication network generally includes a set of parallel wires capable of transmitting data simultaneously.
It is highly desirable for on-chip networks to take up as little area as possible, and so the wires that make up the communication network are typically packed together as closely as allowed by process design rules. The interaction between neighboring wires, specifically the coupling capacitance between neighboring wires, introduces “cross-talk,” a phenomenon that distorts both the timing information and logical voltage levels of data signals traversing the network. This phenomenon is cumulative, and therefore becomes progressively worse across greater distances. At high data rates, this effect severely limits the distance over which data can be transmitted.
Cross-talk can be effectively canceled by shielding the wires that compose the communication network. However, this technique may increase the area of the communication network greatly.
Accordingly, what is needed in the art is a communication network that is more robust against the effects of cross-talk while consuming minimal on-chip area.